Multiprocessor computing systems are being increasingly used in applications which require a large amount of computing capacity. Many types of multiprocessor systems exist, but in general, such systems are characterized by a number of independently running processors which are coupled together over a common bus in order to facilitate the sharing of resources between the processors. Of course, since the bus is common to all processors, and each processor is running independently, it is common for more than one processor to attempt to access the bus at the same time, i.e., the same clock cycle. If more than one processor were to gain control of the bus, then it is likely that data collision from the bus would occur.
Accordingly, it is important that a multiprocessor computer system have the ability to arbitrate simultaneous requests for the bus. Normally, this is performed by assigning priority to one of the requesting processors and allowing it to perform its access. A device which is attempting to gain control of the bus, or which actually controls the bus is sometimes referred to as a "bus master". After the bus master accesses the bus, its priority is removed and passed to another processor requiring access to the bus.
There are numerous ways in which priority can be assigned between the various processors coupled to the bus. However, it is important that the arbitration scheme allow all processors an opportunity to access the bus. Otherwise, repeated accesses by one processor could prevent another processor from obtaining control of the bus and thereby cause impermissible bus latencies in the data stream of the other processors. Accordingly, it is an object of the present invention to provide a bus arbitration method which allows all processors a fair opportunity to access the shared bus. Additional objects and advantages of the present invention will become apparent in view of the following disclosure.